View ISL94200_1252983.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 ? fn6718.0 ISL94200 multi-cell li-ion battery pack ocp/analog front-end the ISL94200 is an overcurrent protection device and analog front end for a microcontroller in a multi-cell li-ion battery pack. the ISL94200 supports battery pack configurations consisting of 4-cells to 7-cells in series and 1 or more cells in parallel. the ISL94200 provides integral overcurrent protection circuitr y, short circuit protection, an internal 3.3v voltage regulator, cell voltage monitor level shifters, and drive circuitry for external fet devices for control of pack charge and discharge. selectable overcurrent and short circuit thresholds reside in internal ram registers. an external microcontroller sets the thresholds by setting register values through an i 2 c serial interface. internal registers al so contain the detection delays for overcurrent and short circuit conditions. using an internal analog multiplexer the ISL94200 provides monitoring of each cell voltage plus internal and external temperature by a separate microcontroller with an a/d converter. software on this microcontroller implements all battery pack control functionality, except for overcurrent and short circuit shutdown. applications ? power tools ? battery backup systems ?e-bikes ? portable test equipment ? medical systems ? hybrid vehicle ? military electronics features ? software selectable overcurrent protection levels and variable protect detection times - 4 discharge overcurrent thresholds - 4 short crcuit thresholds - 4 charge overcurrent thresholds - 8 overcurrent delay times (charge) - 8 overcurrent delay times (discharge) - 2 short circuit delay times (discharge) ? automatic fet turn-off on reaching external (battery) or internal (ic) temperature limit ? fast short circuit pack shutdown ? can use current sense resistor, fet r ds(on) , or sense fet for overcurrent detection ? four battery-backed software controlled flags ? allows three different fet controls: - back-to-back n-channel fets for charge and discharge control - single n-channel discharge fet - single n-channel fet for discharge with separate optional (smaller) back-to-back n-channel fets for charge ? integrated charge/discharge fet drive circuitry with 130a (typ) turn-on current and 180ma (typ) discharge fet turn-off current ? 10% accurate 3.3v voltage regulator (minimum 25ma out with external npn transistor having current gain of 70) ? monitored cell voltage output stable in 100s ?simple i 2 c host interface ? sleep operation with programmable negative edge or positive edge wake-up ? <10a sleep mode ? pb-free (rohs compliant) ordering information part number (note) part marking package (pb-free) pkg. dwg. # ISL94200irz 942 00irtz 24 ld 4x4 qfn l24.4x4d note: these intersil pb-free pl astic packaged products employ special pb-free material sets, molding compounds/die attach materials, and 100% matte tin pl ate plus anneal (e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations). intersil pb-free products are msl classified at pb-free peak reflow te mperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. data sheet july 3, 2008 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2008. all rights reserved all other trademarks mentioned are the property of their respective owners.
2 fn6718.0 july 3, 2008 pinout ISL94200 (24 ld qfn) top view functional diagram scl sda wkup rgc rgo temp3v vcell3 vcell2 vcell1 vss dsense dsref nc vc7/vcc vcell6 vcell5 nc vcell4 tempi ao vmon cfet dfet csense 1 2 3 4 5 6 18 17 16 15 14 13 24 23 22 21 20 19 789101112 3.3vdc regulator vss vc7/vcc csense dsense sda vcell6 vcell5 vcell4 rgo vcell3 fet control circuitry ao vcell2 vcell1 dsref temp3v scl registers rgc wkup power control dfet cfet mux 7 vmon backup supply control logic level shifters cell voltages overcurrent protection circuits (threshold detect and timing) osc temperature sensor, int/ext comparator ext temp enable tempi i 2 c i/f 2 ISL94200
3 fn6718.0 july 3, 2008 pin descriptions symbol description vc7/vcc battery cell 7 voltage input/vcc supply. this pin is used to monitor the voltage of this ba ttery cell externally at pin ao. this pin also provides the operating voltage for the ic circuitry. vcelln battery cell n voltage input. this pin is used to monitor the voltage of this battery cell externally at pin ao. vcelln connects to the positive terminal of celln and the negative terminal of celln + 1. vss ground. this pin connects to the most negative terminal in the battery string. dsref discharge current sense reference. this input provides a separate reference poi nt for the charge and discharge current monitoring circuits. with a separate reference connection, it is possible to minimize errors that result from voltage drops on the ground lead when the load is drawing large currents. if a separate reference is not necessary , connect this pin to vss. dsense discharge current sense monitor. this input monitors the discharge current by monitoring a voltage. it can monitor the voltage across a sense resistor, or the voltage across the dfet, or by us ing a fet with a current sense pin. the voltage on this pin is measured with reference to dsref. csense charge current sense monitor. this input monitors the charge current by monitoring a voltage. it can monitor the voltage across a sense resistor, or the voltage across the cfet, or by using a fe t with a current sense pin. the voltage on this pin is measured with reference to vss. dfet discharge fet control. the ISL94200 controls the gate of a discharge fet through this pin. the power fet is a n-channel device. the fet is turned on only by the microcontroller. the fet can be tu rned off by the microcontroller, but the ISL94200 also turns off the fet in the event of an overcurrent or short circuit condition. if t he microcontroller detects an un dervoltage condition on any of the battery cells, it can turn off the discharge fet by controlling this output with a control bit. cfet charge fet control. the ISL94200 controls the gate of a charge fet through this pin. the power fet is a n-channel device. the fet is turned on only by the microcontr oller. the fet can be turned off by the mi crocontroller, but the ISL94200 also turns off the fet in the event of an overcurrent condition. if the microcontroller detects an overvoltage condition on any of the battery cells, it can turn off the fet by controlling this output with a control bit. vmon discharge load monitoring. in the event of an overcurrent or s hort circuit condition, the microcontro ller can enable an internal resistor that connects between the vmon pin and vss. when the fets open bec ause of an overcurrent or shor t circuit condition and the loa d remains, the voltage at vmon will be near the vcc voltage. when th e load is released, the voltage at vmon drops below a thresho ld indicating that the overcurrent or short ci rcuit condition is resolved. at this poin t, the ldfail flag is cleared and operation can resume. ao analog multiplexer output. the analog output pin is used by an external microcon troller to monitor the cell voltages and temperature sensor voltages. the microcontroller selects the specific voltage being applied to the output by writing to a control register. temp3v temperature monitor output control. this pin outputs a voltage to be used in a divider that consists of a fixed resistor and a thermistor. the thermistor is located in close proximity to the cells. the temp3v output is connected internally to the rgo vol tage through a pmos switch only during a measurement of the temperatur e, otherwise the temp3v output is off. the temp3v output can be turned on continuously with a special control bit. microcontroller wake up control. the temp3v pi n is also turned on when any of the dsc, doc, or coc bits are set. this can be us ed to wake up a sleeping microcontroller to respond to ov ercurrent conditions with its own control mechanism. tempi temperature monitor input. this pin inputs the voltage across a thermistor to det ermine the temperature of the cells. when this input drops below temp3v/13, an external over-temperature condition exis ts. the tempi voltage is also fed to the ao output pin throug h an analog multiplexer so the temperature of the cells can be monitored by the microcontroller. rgo regulated output voltage. this pin connects to the emitter of an external npn transistor and works in conjunction with the rgc pin to provides a regulated 3.3v. the voltage at this pin provides feedback for the regulator and power for many of the ISL94200 in ternal circuits as well as providing the 3.3v output voltag e for the microcontroller and other external circuits. rgc regulated output control. this pin connects to the base of an external npn transistor and works in conjunction with the rgo pin to provide a regulated 3.3v. the rgc output provides the control si gnal for the external transistor to provide the 3.3v regulated voltage on the rgo pin. wkup wake up voltage. this input wakes up the part when the voltage cros ses a turn-on threshold (wake up is edge triggered). the condition of the pin is reflected in the wk up bit (the wkup bit is level sensitive.) wkpol bit = ?1?: the device wakes up on the rising edge of the wk up pin. also, the wkup bit is high only when the wkup pin voltage > threshold. wkpol bit = ?0?, the device wakes up on the falling edge of the wk up pin. also, the wkup bit is high only when the wkup pin voltage < threshold. sda serial data. this is the bidirectional data line for an i 2 c interface. scl serial clock. this is the clock input for an i 2 c communication link. ISL94200
4 fn6718.0 july 3, 2008 absolute maximum rati ngs thermal information power supply voltage, vcc . . . . . . . . . .v ss - 0.5v to v ss + 36.0v cell voltage, vcell vcelln - (vcelln - 1), vcell1 - vss. . . . . . . . . . . -0.5v to 5v terminal voltage, v term1 (scl, sda, c sense , d sense , tempi, rgo, ao, temp3v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v ss - 0.5 to v rgo + 0.5v terminal voltage, v term2 (cfet, vmon) . . . . v ss - 22.0v to v cc terminal voltage, v term3 (wkup) . . . . . . . . . . . . . . . . . . . . . . . . . . . v ss - 0.5v to v cc (v cc <27v) terminal voltage, v term4 (rgc) . . . . . . . . . . . . . v ss - 0.5v to 5v terminal voltage, v term5 , (all other pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v ss - 0.5v to v cc +0.5v thermal resistance (typical, notes 1, 2) ja (c/w) jc (c/w) 24 ld qfn . . . . . . . . . . . . . . . . . . . . . . 32 2 continuous package power dissipation . . . . . . . . . . . . . . . . .400mw storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . -55 to +125c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp operating conditions temperature range . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +85c supply voltage range (typical). . . . . . . . . . . . . . . . . . . . 5v to 10v operating voltage: vcc pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2v to 30.1v vcell1 - vss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3v to 4.3v vcelln - (vcelln - 1) . . . . . . . . . . . . . . . . . . . . . . 2.3v to 4.3v caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 1. ja is measured in free air with the component mounted on a high ef fective thermal conductivity te st board with ?direct attach? fe atures. see tech brief tb379. 2. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. operating specifications over the recommended operating conditions unless otherwi se specified. parameters with min and/or max limits are 100% tested at +25c, unless otherwise specif ied. temperature limits es tablished by characterization and are not production tested. parameter symbol test condition min typ max unit operating voltage v cc 9.2 30.1 v power-up condition 1 v porvcc v cc voltage (note 3) 4 9.2 v power-up condition 2 threshold v por123 v cell1 - v ss and v cell2 - v cell1 and v cell3 - v cell2 (rising) (note 3) 1.1 1.7 2.3 v power-up condition 2 hysteresis v porhys v cell1 - v ss and v cell2 - v cell1 and v cell3 - v cell2 (falling) (note 3) 70 mv 3.3v regulated voltage v rgo 0a < i rgc < 350a 3.0 3.3 3.6 v 3.3vdc voltage regulator control current limit i rgc (control current at output of rgc. recommend npn with gain of 70+) 0.35 0.50 ma v cc supply current i vcc1 power-up defaults, wkup pin = 0v. 400 510 a rgo supply current i rgo1 power-up defaults, wkup pin = 0v. 300 410 a v cc supply current i vcc2 ldmonen bit = 1, vmon floating, cfet = 1, dfet=1, wkpol bit = 1, vwkup = 10v, [ao3:ao0] bits = 03h. 500 700 a rgo supply current i rgo2 ldmonen bit = 1, vmon floating, cfet = 1, dfet=1, wkpol bit = 1, vwkup = 10v, [ao3:ao0] bits = 03h. 450 650 a v cc supply current i vcc3 default register settings, except sleep bit = 1. wkup pin = vcell1 10 a rgo supply current i rgo3 default register settings, except sleep bit = 1. wkup pin = vcell1 1a vcell input current (v cell1 )i vcell1 ao3:ao0 bits = 0000h 14 a vcell input current (v celln )i vcelln ao3:ao0 bits = 0000h 10 a ISL94200
5 fn6718.0 july 3, 2008 overcurrent/short circuit protection specifications overcurrent detection threshold (discharge) voltage relative to dsref (default in boldface) v ocd v ocd = 0.10v (ocdv1, ocdv0 = 0, 0) 0.08 0.10 0.12 v v ocd = 0.12v (ocdv1, ocdv0 = 0,1) 0.10 0.12 0.14 v v ocd = 0.14v (ocdv1, ocdv0 = 1,0) 0.12 0.14 0.16 v v ocd = 0.16v (ocdv1, ocdv0 = 1,1) 0.14 0.16 0.18 v overcurrent detection threshold (charge) voltage relative to dsref (default in boldface) v occ v occ = 0.10v (occv1, occv0 = 0, 0) -0.12 -0.10 -0.07 v v occ = 0.12v (occv1, occv0 = 0,1) -0.14 -0.12 -0.09 v v occ = 0.14v (occv1, occv0 = 1,0) -0.16 -0.14 -0.11 v v occ = 0.16v (occv1, occv0 = 1,1) -0.18 -0.16 -0.13 v short current detection threshold voltage relative to dsref (default in boldface) v sc v oc = 0.20v (scdv1, scdv0 = 0, 0) 0.15 0.20 0.25 v v oc = 0.35v (scdv1, scdv0 = 0,1) 0.30 0.35 0.40 v v oc = 0.65v (scdv1, scdv0 = 1, 0) 0.60 0.65 0.70 v v oc = 1.20v (scdv1, scdv0 = 1,1) 1.10 1.20 1.30 v load monitor input threshold (falling edge) v vmon ldmonen bit = ?1? 1.1 1.45 1.8 v load monitor input threshold (hysteresis) v vmonh ldmonen bit = ?1? 0.25 mv load monitor current i vmon 20 40 60 a short circuit time-out t scd short circuit detection delay (sclong bit = ?0?) 90 190 290 s short circuit detection delay (sclong bit = ?1?) 51015ms over discharge current time-out (default in boldface) t ocd t ocd = 160ms (ocdt1, ocdt0 = 0, 0 and dtdiv = 0) 80 160 240 ms t ocd = 320ms (ocdt1, ocdt0 = 0, 1 and dtdiv = 0) 160 320 480 ms t ocd = 640ms (ocdt1, ocdt0 = 1, 0 and dtdiv = 0) 320 640 960 ms t ocd = 1280ms (ocdt1, ocdt0 = 1, 1 and dtdiv = 0) 640 1280 1920 ms t ocd = 2.5ms (ocdt1, ocdt0 = 0, 0 and dtdiv = 1) 1.25 2.50 3.75 ms t ocd = 5ms (ocdt1, ocdt0 = 0, 1 and dtdiv = 1) 2.5 5 7.5 ms t ocd = 10ms (ocdt1, ocdt0 = 1, 0 and dtdiv = 1) 51015ms t ocd = 20ms (ocdt1, ocdt0 = 1, 1 and dtdiv = 1) 10 20 30 ms operating specifications over the recommended operating conditions unless otherwi se specified. parameters with min and/or max limits are 100% tested at +25c, unless otherwise specif ied. temperature limits es tablished by characterization and are not production tested. (continued) parameter symbol test condition min typ max unit ISL94200
6 fn6718.0 july 3, 2008 ISL94200 over charge current time-out (default in boldface) t occ t occ = 80ms (occt1,occt0 = 0, 0 and ctdiv = 0) 40 80 120 ms t occ = 160ms (occt1, occt0 = 0, 1 and ctdiv = 0) 80 160 240 ms t occ = 320ms (occt1, occt0 = 1, 0 and ctdiv = 0) 160 320 480 ms t occ = 640ms (occt1, occt0 = 1, 1 and ctdiv = 0) 320 640 960 ms t occ = 2.5ms (occt1, occt0 = 0, 0 and ctdiv = 1) 1.25 2.50 3.75 ms t occ = 5ms (occt1, occt0 = 0, 1 and ctdiv = 1) 2.5 5 7.5 ms t occ = 10ms (occt1, occt0 = 1, 0 and ctdiv = 1) 51015ms t occ = 20ms (occt1, occt0 = 1, 1 and ctdiv = 1) 10 20 30 ms over-temperature protection specifications internal temperature shutdown threshold t intsd +125 c internal temperature hysteresis t hys temperature drop needed to restore operation after over-temperature shutdown. +20 c internal over-temperature turn on delay time t itd 128 ms external temperature output current i xt current output capability at temp3v pin 1.2 ma external temperature limit threshold t xtf voltage at v tempi ; relative to falling edge -20 0 +20 mv external temperature limit hysteresis t xth voltage at v tempi . 60 110 160 mv external temperature monitor delay t xtd delay between activating the external sensor and the internal over-temperature detection. 1ms external temperature autoscan on-time t xtaon temp3v is on (3.3v) 5 ms external temperature autoscan off-time t xtaoff temp3v output is off. 635 ms analog output specifications cell monitor analog output voltage accuracy v aoc [v celln - (v celln-1 )]/2 - ao -15 4 30 mv cell monitor analog output external temperature accuracy v aoxt external temperature monitoring accuracy. voltage error at ao when monitoring tempi voltage (measured with tempi = 1v) -10 10 mv internal temperature monitor output voltage slope v intmon internal temperature monitor voltage change -3.5 mv/c operating specifications over the recommended operating conditions unless otherwi se specified. parameters with min and/or max limits are 100% tested at +25c, unless otherwise specif ied. temperature limits es tablished by characterization and are not production tested. (continued) parameter symbol test condition min typ max unit v temp3v 13 ------------------------------
7 fn6718.0 july 3, 2008 internal temperature monitor output t int25 output at +25c 1.31 v ao output stabilization time t vsc from scl falling edge at data bit 0 of command to ao output stable within 0.5% of final value. ao voltage steps from 0v to 2v. (c ao = 10pf) (note 7) 0.1 ms wake up/sleep specifications device wkup pin voltage threshold (wkup pin active high - rising edge) v wkup1 wkup pin rising edge (wkpol = 1) device wakes up and sets wkup flag high. 3.5 5.0 6.5 v device wkup pin hysteresis (wkup pin active high) v wkup1h wkup pin falling edge hysteresis (wkpol = 1) sets wkup flag low (does not automatically enter sleep mode) 100 mv input resistance on wkup r wkup resistance from wkup pin to vss (wkpol = 1) 130 230 330 k device wkup pin active voltage threshold (wkup pin active low - falling edge) v wkup2 wkup pin falling edge (wkpol = 0) device wakes up and sets wkup flag high. v cell1 -2.6 v cell1 -2.0 v cell1 -1.2 v device wkup pin hysteresis (wkup pin active low) v wkup2h wkup pin rising edge hysteresis (wkpol = 0) sets wkup flag low (does not automatically enter sleep mode) 200 mv device wake-up delay t wkup delay after voltage on wkup pin crosses the threshold (rising or falling) before activating the wkup bit. 20 40 60 ms fet control specifications (for vcell1, vcell2, vcell3 voltages from 2.8v to 4.3v) control outputs response time (cfet, dfet) t co bit 0 to start of control signal (dfet) bit 1 to start of control signal (cfet) 1.0 s cfet gate voltage vcfet no load on cfet v cell3 -0.5 v cell3 +0.1 v dfetgate voltage vdfet no load on dfet v cell3 -0.5 v cell3 +0.1 v fet turn on current (dfet) i dfon dfet voltage = 0 to vcell3 -1.5v 80 130 400 a fet turn on current (cfet) i cf(on) cfet voltage = 0 to vcell3 - 1.5v 80 200 400 a fet turn off current (dfet) i df(off) dfet voltage = vdfet to 1v 100 180 ma dfet resistance to vss r df(off) vdfet <1v (when turning off the fet) 11 serial interface characteristics scl clock frequency f scl 100 khz pulse width suppression time at sda and scl inputs t in any pulse narrower than the max spec is suppressed. 50 ns scl falling edge to sda output data valid t aa from scl falling crossing v ih (min), until sda exits the v il (max) to v ih (min) window. 3.5 s time the bus must be free before start of new transmission t buf sda crossing v ih (min) during a stop condition to sda crossing v ih (min) during the following start condition. 4.7 s clock low time t low measured at the v il (max) crossing. 4.7 s clock high time t high measured at the v ih (min) crossing. 4.0 s operating specifications over the recommended operating conditions unless otherwi se specified. parameters with min and/or max limits are 100% tested at +25c, unless otherwise specif ied. temperature limits es tablished by characterization and are not production tested. (continued) parameter symbol test condition min typ max unit ISL94200
8 fn6718.0 july 3, 2008 start condition setup time t su:sta scl rising edge to sda falling edge. both crossing the v ih (min) level. 4.7 s start condition hold time t hd:sta from sda falling edge crossing v il (max) to scl falling edge crossing v ih (min). 4.0 s input data setup time t su:dat from sda exiting the v il (max) to v ih (min) window to scl rising edge crossing v il (min). 250 ns input data hold time t hd:dat from scl falling edge crossing v ih (min) to sda entering the v il (max) to v ih (min) window. 300 s stop condition setup time t su:sto from scl rising edge crossing v ih (min) to sda rising edge crossing v il (max). 4.0 s stop condition hold time t hd:sto from sda rising edge to scl falling edge. both crossing v ih (min). 4.0 s data output hold time t dh from scl falling edge crossing v il (max) until sda enters the v il (max) to v ih (min) window. (note 4) 0ns sda and scl rise time t r from v il (max) to v ih (min). 1000 ns sda and scl fall time t f from v ih (min) to v il (max). 300 ns capacitive loading of sda or scl (note 5) cb total on-chip and off-chip 400 pf sda and scl bus pull-up resistor- off-chip (note 5) r out maximum is determined by t r and t f . for c b = 400pf, max is about 2k ~ 2.5k for c b = 40pf, max is about 15k to 20k 1k input leakage current (scl, sda) i li -10 10 a input buffer low voltage (scl, sda) v il voltage relative to v ss of the device. -0.3 v rgo x 0.3 v input buffer high voltage (scl, sda) v ih voltage relative to v ss of the device. v rgo x 0.7 v rgo +0.1 v output buffer low voltage (sda) v ol i ol = 1ma 0.4 v sda and scl input buffer hysteresis (note 5) i 2 chyst sleep bit = 0 0.05 * v rgo v notes: 3. power-up of the device requires all v cell1 , v cell2 , v cell3 , and vcc to be above the limits specified. 4. the device provides an internal hold time of at least 300ns for the sda signal to bridge the unidentified region of the falli ng edge of scl. 5. limits should be considered typical and are not production tested. 6. typical 5 2 , based on characterization data. 7. maximum output capacitance = 15pf. operating specifications over the recommended operating conditions unless otherwi se specified. parameters with min and/or max limits are 100% tested at +25c, unless otherwise specif ied. temperature limits es tablished by characterization and are not production tested. (continued) parameter symbol test condition min typ max unit ISL94200
9 fn6718.0 july 3, 2008 wake-up timing (wkpol = 0) wake up timing (wkpol = 1) change in voltage source, fet control v wkup2 v wkup2h t wkup t wkup ISL94200
10 fn6718.0 july 3, 2008 automatic temperature scan discharge overcurrent/ short circuit monitor (assumes denocd and denscd bits are ?0?) auto temp control (internal activation) temp3v pin tmp3v/13 delay time = 1ms 635ms monitor time = 5ms 3.3v xot bit external over-temperature delay time = 1ms fet shutdown turn off monitor temp during this high impedance time period threshold temperature (if enabled) v sc v ocd t scd t ocd t scd doc bit dsc bit temp3v v dsense register 1 read register 1 read output 3.3v ?1? ?1? ?0? ?0? dfet output c turns on dfet vcell3 ISL94200
11 fn6718.0 july 3, 2008 charge overcurrent monitor (assumes denocc bit is ?0?) serial interface timing diagrams bus timing symbol table v occ t occ coc bit temp3v v csense register 1 read output 3.3v ?1? ?0? cfet output c turns on cfe 12v t su:sto t high t su:sta t hd:sta t hd:dat t su:dat scl t f t low t buf t r t dh t aa sda (input timing) sda (output timing) waveform inputs outputs must be steady will be steady may change from low to high will change from low to high may change from high to low will change from high to low don?t care: changes allowed changing: state not known n/a center line is high impedance waveform inputs outputs ISL94200
12 fn6718.0 july 3, 2008 registers table 1. registers addr register read/write 7 6 5 4 3 2 1 0 00h config/op status read only reserved reserved sa single afe wkup wkup pin status reserved reserved reserved reserved 01h operating status (note 10) read only reserved reserved xot ext over temp iot int over te m p ldfail load fail (vmon) dsc short circuit doc discharge oc coc charge oc 02h not used read/write reserved reserved reserved reserved reserved reserved reserved reserved 03h analog out read/write uflg1 user flag 1 uflg0 user flag 0 reserved reserved ao3 ao2 ao1 ao0 analog output select bits 04h fet control read/write sleep force sleep (note 11) ldmonen turn on vmon connection reserved reserved reserved reserved cfet turn on charge fet (note 12) dfet turn on discharge fet (note 12) 05h discharge set read/write (write only if disseten bit set) denocd ocdv1 ocdv0 denscd scdv1 scdv0 ocdt1 ocdt0 turn off automatic ocd control overcurrent discharge threshold voltage turn off automatic scd control short circuit discharge threshold voltage overcurrent discharge time-out 06h charge set read/write (write only if chseten bit set) denocc occv1 occv0 sclong long short- circuit delay ctdiv divide charge time by 32 dtdiv divide discharge time by 64 occt1 occt0 turn off automatic occ control overcurrent charge threshold voltage overcurrent charge time-out 07h feature set read/write (write only if fseten bit set) atmpoff turn off automatic external temp scan dis3 disable 3.3v reg. (device requires external 3.3v) tmp3on turn on temp3v disxtsd disable external thermal shutdown disitsd disable internal thermal shutdown por force por diswkup disable wkup pin wkpol wake up polarity 08h write enable read/write fseten enable feature set writes chseten enable charge set writes disseten enable discharge set writes uflg3 user flag 3 uflg2 user flag 2 reserved reserved reserved 09h:ffh reserved na reserved notes: 8. a ?1? written to a control or configuration bit causes the acti on to be taken. a ?1? read from a status bit indicates that th e condition exists. 9. ?reserved? indicates that the bit or regi ster is reserved for future expansion. when writing to addresses 2, 3, 4, and 8: wri te a reserved bit with the value ?0?. do not write to reserved registers at addresses 09h through ffh. ignore reserved bits that are returned in a rea d operation. 10. these status bits are automatically cleared when the register is read. all other status bits are cleared when the condition is cleared. 11. this sleep bit is cleared on initial power up, by the wkup pin going high (when wkpol = ?1?) or by the wkup pin going low (whe n wkpol = ?0?), and by writing a ?0? to the location with an i 2 c command. 12. when the automatic responses are enabled, these bits are autom atically reset by hardware when an overcurrent or short circui t condition turns off the fets. at all other times, an i 2 c write operation controls the output to the respective fet and a read returns the current state of the fet drive output circuit (though not the actual voltage at the output pin.) ISL94200
13 fn6718.0 july 3, 2008 status registers table 2. config/op status register (addr: 00h) bit function description 7 reserved reserved for future expansion. 6 reserved reserved for future expansion. 5sa single afe indicates the device is an ISL94200. this bit is set in the chip and cannot be changed. 4 wkup wakeup pin status this bit is set and reset by hardware. when ?wkpol? is high: ?wkup? high = wkup pin > threshold voltage ?wkup? low = wkup pin < threshold voltage when ?wkpol? is low: ?wkup? high = wkup pin < threshold voltage ?wkup? low = wkup pin > threshold voltage 3 reserved reserved for future expansion. 2 reserved reserved for future expansion. 1 reserved reserved for future expansion. 0 reserved reserved for future expansion. table 3. operating status register (addr: 01h) bit function description 7 reserved reserved for future expansion. 6 reserved reserved for future expansion. 5xot ext over-temp this bit is set to ?1? when the external thermistor indicates an over-temperature condition. if the temperature condition has cleared, this bit is reset when the register is read. 4iot int over-temp this bit is set to ?1? when the internal thermistor indica tes an over-temperature condition. if the temperature condition has cleared, this bit is rese t when the register is read. 3 ldfail load fail (vmon) when the function is enabled, this bit is set to ?1? by har dware when a discharge overcurrent or short circuit condition occurs and the load remains heavy. when the load fail conditi on is cleared or under a light load, the bit is reset when the register is read. 2dsc short circuit this bit is set by hardware when a s hort circuit condition occurs during discharge. when t he discharge short circuit condition is removed, the bit is reset when the register is read. 1doc discharge oc this bit is set by hardware when an overcurrent condition occurs during discharge. when the discharge overcurrent condition is removed, the bit is reset when the register is read. 0coc charge oc this bit is set by hardware when an overcurrent conditi on occurs during charge. when the charge overcurrent condition is removed, the bit is reset when the register is read. ISL94200
14 fn6718.0 july 3, 2008 control registers configuration registers the device is configured fo r specific application requirements using the conf iguration registers. the configuration registers consist of sram memory. this memory is powered by the rgo output. in a sleep condition, an internal switch converts power for the contents of these registers from rgo to the vcell1 input. table 4. analog out control register (addr: 03h) bits function description 7uflg1 user flag 1 general purpose flag usable by mi crocontroller software. this bit is battery backed up, even when rgo turns off. 6uflg0 user flag 0 general purpose flag usable by mi crocontroller software. this bit is battery backed up, even when rgo turns off. 5:4 reserved reserved for future expansion bit 3 ao3 bit 2 ao2 bit 1 ao1 bit 0 ao0 output voltage 0 0 0 0 no output (low power state) 0001v cell1 0010v cell2 0011v cell3 0100v cell4 0101v cell5 0110v cell6 0111v cell7 1 0 0 0 external temperature 1 0 0 1 internal temperature 1 x 1 x reserved 1 1 x x reserved table 5. fet control register (addr: 04h) bit function description 7 sleep force sleep setting this bit to ?1? forces the device to go into a sleep condition. this turns off both fet outputs and the voltage regulator. this also resets the cfet, dfet, and cb7on:cb1on bits. the sleep bit is automatically reset to ?0? when the device wakes up. this bit does not reset the ao3:ao0 bits. 6ldmonen turn on vmon connection writing a ?1? to this bit turns on the vmon circuit. writing a ?0? to this bit turns off the vmon circuit. as such, the microcontroller has full control of the operation of this circuit. 5:2 reserved reserved for future expansion. 1cfet setting this bit to ?1? turns on the charge fet. setting this bit to ?0? turns off the charge fet. this bit is automatically rese t in the event of a charge ov ercurrent condition, unless the automatic response is dis abled by the denocc bit. 0dfet setting this bit to ?1? turns on the discharge fet. setting this bit to ?0? turns off the discharge fet. this bit is automatically reset in the event of a discharge overcurrent or discharge short circuit condition, unless the automatic response is disabled by the denocd or denscd bits. ISL94200
15 fn6718.0 july 3, 2008 table 6. discharge set configuration register (addr: 05h) setting function bit 7 denocd turn off automatic oc discharge control when set to ?0?, a discharge overcurrent co ndition automatically turns off the fets. when set to ?1?, a discharge overcurrent conditi on will not automatically turn off the fets. in either case, this condition sets the do c bit, which also turns on the temp3v output. bit 6 ocdv1 bit 5 ocdv0 overcurrent discharge voltage threshold 00v ocd = 0.10v 01v ocd = 0.12v 10v ocd = 0.14v 11v ocd = 0.16v bit 4 denscd turn off automatic sc discharge control when set to ?0?, a discharge short circuit condition turns off the fets. when set to ?1?, a discharge short circuit conditi on will not automatically turn off the fets. in either case, the condition sets the scd bit, which also turns on the temp3v output. bit 3 scdv1 bit 2 scdv0 short circuit discharge voltage threshold 00v scd = 0.20v 01v scd = 0.35v 10v scd = 0.65v 11v scd = 1.20v bit 1 ocdt1 bit 0 ocdt0 overcurrent discharge time-out 00t ocd = 160ms (2.5ms if dtdiv = 1) 01t ocd = 320ms (5ms if dtdiv = 1) 10t ocd = 640ms (10ms if dtdiv = 1) 11t ocd = 1280ms (20ms if dtdiv = 1) ISL94200
16 fn6718.0 july 3, 2008 table 7. charge/time scale config register (addr: 06h) setting function bit 7 denocc turn off automatic oc charge control when set to ?0?, a charge overcurrent c ondition automatically turns off the fets. when set to ?1?, a charge overcurrent condit ion will not automatical ly turn off the fets. in either case, this condition sets the coc bit, which also turns on the temp3v output. bit 6 occv1 bit 5 occv0 overcurrent charge voltage threshold 00v ocd = 0.10v 01v ocd = 0.12v 10v ocd = 0.14v 11v ocd = 0.16v bit 4 sclong short circuit long delay when this bit is set to ?0?, a short circuit needs to be in effect for 190us before a shutdown begins. when this bit is set to ?1?, a short circuit needs to be in effect for 10ms before a shutdown begins. bit 3 ctdiv divide charge time by 32 when set to ?1?, the charge overcu rrent delay time is divided by 32. when set to ?0?, the charge overcu rrent delay time is divided by 1. bit 2 dtdiv divide discharge time by 64 when set to ?1?, the discharge overcurrent delay time is divided by 64. when set to ?0?, the discharge overcurrent delay time is divided by 1. bit 1 occt1 bit 0 occt0 overcurrent charge time-out 00t occ = 80ms (2.5ms if ctdiv=1) 01t occ = 160ms (5ms if ctdiv=1) 10t occ = 320ms (10ms if ctdiv=1) 11t occ = 640ms (20ms if ctdiv=1) table 8. feature set configuration register (addr: 07h) bit function description 7 atmpoff turn off automatic external temp scan when set to ?1? this bit disables the automatic te mperature scan. when set to ?0?, the temperature is turned on for 5ms in every 640ms. 6dis3 disable 3.3v regulator setting this bit to ?1? disables t he internal 3.3v regulator. setting this bit to ?1? requires that there be an external 3.3v regulator connected to the rgo pin. 5tmp3on turn on temp 3.3v setting this bit to ?1? turns on the temp3v output to the external temperature sensor. the output will remain on as long as this bit remains ?1?. 4 disxtsd disable external thermal shutdown setting this bit to ?1? disables the automatic shutdown of the power fets in response to an external over-temperature condition. while the automatic response is di sabled, the xot flag is set so the microcontroller can initiate a shutdown based on the xot flag. 3 disitsd disable internal thermal shutdown setting this bit to ?1? disables the automatic shutdown of the power fets in response to an internal over-temperature condition. while the aut omatic response is dis abled, the iot flag is set so the microcontroller can initiate a shutdown based on the iot flag. 2por force por setting this bit to ?1? forces a por condition. this resets all internal registers to zero. 1 diswkup disable wkup pin setting this bit to ?1? dis ables the wkup pin function. caution: setting this pin to ?1? prevents a wake up condition. if the device then goes to sleep, it cannot be waken without a communication link that resets this bit, or by power cycling the device. 0wkpol wake up polarity setting this bit to ?1? sets the device to wake up on a rising edge at the wkup pin. setting this bit to ?0? sets the device to wake up on a falling edge at the wkup pin. ISL94200
17 fn6718.0 july 3, 2008 . device description design theory instructed by the microcontroll er, the ISL94200 performs cell voltage monitoring operations, overcurrent and short circuit monitoring with automatic pack shutdown using built-in selectable time delays, and automatic turn off of the power fets in an over-temperature condition. all automatic functions of the ISL94200 can be turned off and the microcontroller can manage the operations through software. battery connection the ISL94200 supports packs of 5 to 7 series connected li-ion cells. connection guidelines for each cell combination are shown in figure 1. system power-up/power-down the ISL94200 powers up when the voltages on v cell1 , v cell2 , v cell3 , and vcc all exceed their por threshold. at this time, the ISL94200 wakes up and turns on the rgo output. rgo provides a regulated 3. 3vdc 10% voltage at pin rgo. it does this by using a control voltage on the rgc pin to drive an external npn transistor (see figure 2.) the transistor should have a beta of at least 70 to provide ample current to the device and external circuits and should have a v ce of greater than 30v (preferably 50v). the voltage at the emitter of the npn transistor is monitored and regulated to 3.3v by the control signal rg c. rgo also powers most of the ISL94200 internal circuits. a 500 resistor is recommended in the collector of the npn transistor to minimize initial current surge when the regulator turns on. once powered up, the device remains in a wake up state until put to sleep by the microcontroller (typically when the cells drop too low in voltage) or until the v cell1 , v cell2 , v cell3 , or vcc voltages drop below their por threshold. table 9. write enable register (addr: 08h) bit function description 7 fseten enable discharge set writes when set to ?1?, allows writes to the feature set regi ster. when set to ?0?, prevents writes to the feature set register (addr: 07h). default on initial power up is ?0?. 6 chseten enable charge set writes when set to ?1?, allows writes to the charge set regist er. when set to ?0?, prevents writes to the feature set register (addr: 06h). default on initial power up is ?0?. 5 disseten enable discharge set writes when set to ?1?, allows writes to the discharge set register (addr: 05h). when set to ?0?, prevents writes to the feature set register. default on initial power up is ?0?. 4uflg3 user flag 3 general purpose flag usable by microcontroller softwa re. this bit is battery backed up, even when rgo turns off. 3uflg2 user flag 3 general purpose flag usable by microcontroller softwa re. this bit is battery backed up, even when rgo turns off. 2 reserved reserved for future expansion. 1 reserved reserved for future expansion. 0 reserved reserved for future expansion. vcell7 vcell6 vcell5 vcell4 vcell3 vcell2 vcell1 vss 7 cells vcell7 vcell6 vcell5 vcell4 vcell3 vcell2 vcell1 vss 6 cells vcell7 vcell6 vcell5 vcell4 vcell3 vcell2 vcell1 vss 5 cells figure 1. battery connection options note: multiple cells can be connected in parallel rgc rgo vss vcc 3.3v gnd figure 2. voltage regulator circuits 500 ISL94200
18 fn6718.0 july 3, 2008 wkup pin operation there are two ways to design a wake up of the ISL94200. in an active low connection (w kpol = ?0? - default), the device wakes up when a charger is connected to the pack. this pulls the wkup pin low when compared to a reference based on the v cell1 voltage. in an active high connection (wkpol = ?1?) the device wakes up when the wkup pin is pulled high by a connection through an external switch. protection functions in the default recommended condition, the ISL94200 automatically responds to discharge overcurrent, discharge short circuit, charge overcurr ent, internal over-temperature, and external over-temperature conditions. the designer can set optional over-ride conditions that allow the response to be dictated by the microcontro ller. these are discussed below. overcurrent safety functions the ISL94200 continually monito rs the discharge current by monitoring the voltage at the csense and dsense pins. if that voltage exceeds a selected value for a time exceeding a selected delay, then the device en ters an overcurrent or short circuit protection mode. in these modes, the ISL94200 automatically turns off both po wer fets and hence prevents current from flowing through the terminals p+ and p-. the voltage thresholds and the response times of the overcurrent protection circuits are selectable for discharge overcurrent, charge overcurrent, and discharge short circuit conditions. the specific settings are determined by bits in the discharge set configurati on register (addr:05h) (refer to table 6) and the charge/time scale configuration scale register (addr:06h) (refer to table 7). in addition, refer to ?registers? on page 12. in an overcurrent condition, th e ISL94200 automatically turns off the voltage on cfet and dfet pins. the dfet output drives the discharge fet gate low, turning off the fet quickly. the cfet output turns off and allows the gate of the charge fet to be pulled low through a resistor. by turning off the fets the ISL94200 prevents damage to the battery pack caused by excessive cu rrent into or out of the cells (as in the case of a faulty char ger or short-circuit condition). when the ISL94200 detects a disc harge overcurrent condition, both power fets are turned off and the doc bit is set. (when the fets are turned off, the dfet and cfet bits are also reset.) the automatic response to overcurrent during discharge is prevented by setting the de nocd bit to ?1?. the external microcontroller can turn on the fets at any time to recover from this condition, but it would usually turn on the load monitor function (by setting the ldmone n bit) and monitor the ldfail bit to detect that the overcu rrent condition has been removed. when the ISL94200 detects a discharge short circuit condition, both power fets are turned off and dsc bit is set. (when the fets are turned off, the dfet and cfet bits are also reset.) the automatic response to short circuit during discharge is prevented by setting the denscd bit to ?1?. the external microcontroller can turn on the fets at any time to recover from this condition, but it would usually turn on the load monitor function (by setting the ldmone n bit) and monitor the ldfail bit to detect that the overcu rrent condition has been removed. when the ISL94200 detects a char ge overcurrent condition, both power fets are turned off and coc bit is set. (when the fets are turned off, the dfet and cfet bits are also reset.) the automatic response to overcurrent during discharge is prevented by setting the denocc bit to ?1?. the external microcontroller can turn on the fets at any time to recover from this condition, but it would usually wait to do this until the cell voltages are not over charged and that the overcurrent condition has been removed. or, the microcontroller could wait until the pack is removed from the charger and then re-attached. an alternative method of provid ing the protection function, if desired by the designer, is to turn off the automatic safety response. in this ca se, the ISL94200 devices still monitor the conditions and set the status bits, but take no action in overcurrent or short circuit conditions. safety of the pack depends, instead, on the microcontroller to send commands to the ISL94200 to turn off the fets. to facilitate a microcontroller response to an overcurrent condition, especially if the mi crocontroller is in a low power state, a charge overcurrent flag (coc), a discharge overcurrent flag (doc), or the short circuit flag (dsc) being set causes the ISL94200 temp3v output to turn on and pull high (see figure 5). this output can be used as an external interrupt by the microcontroller to wake-up quickly to handle the overcurrent condition. ISL94200 figure 3. wake up control circuits vss 230k* * internal resistor only connected when wkpol = 1. 5v wkup wkpol wkup (status) (control) wake up circuits v cell1 ISL94200
19 fn6718.0 july 3, 2008 load monitoring the load monitor function in the ISL94200 (see figure 4) is used primarily to detect that the load has been removed following an overcurrent or short circuit condition during discharge. this can be used in a control algorithm to prevent the fets from turning on while the overload or short circuit condition remains. the load monitor can also be used by the microcontroller algorithms after an undervoltage condition on any cells causes the fets to turn off. use of the load monitor prevents the fets from turning on while the load is still present. this minimizes the possible ?oscillations? that can occur when a load is applied in a low capacity pack. it can also be part of a system protection mechanism to prevent the load from turning on automatically - i.e. some action must be taken before the pack is again turned on. the load monitor circuit can be turned on or off by the microcontroller. it is normally tu rned off to minimize current consumption. it must be ac tivated by the external microcontroller for it to op erate. the circuit works by internally connec ting the vmon pin to vss through a resistor. the circuit operates shown as in figure 4. in a typical pack operation, when an overcurrent or short circuit event happens, the dfet turns off, opening the battery circuit to the load. at this time, the r l is small and the load monitor is initially off. in this condition, the voltage at vmon rises to nearly the pack voltage. once the power fets turn off, the microcontroller activates the load monitor by setting the ldmonen bit. this turns on an internal fet that adds a pull down resistor to the load monitor circuit. while still in the overload condition the combination of the load resist or, an external adjustment resistor (r 1 ), and the internal load monitor resistor form a voltage divider. r 1 is chosen so that when the load is released to a sufficient level, the ldfail condition is reset. over-temperature safety functions external temperature monitoring the external temperature is monitored by using a voltage divider consisting of a fixed resistor and a thermistor. this divider is powered by the ISL94200 temp3v output. this output is normally controlled so it is on for only short periods to minimize current consumption. without microcontroller intervent ion, and in the default state, the ISL94200 provides an automa tic temperature scan. this scan circuit repeatedly turns on temp3v output (and the external temperature monitor) for 5ms out of every 640ms. in this way, the external temper ature is monitored even if the microcontroller is asleep. when the temp3v output turns on, the ISL94200 waits 1ms for the temperature reading to stabilize, then compares the external temperature voltage with an internal voltage divider that is set to temp3v/13. w hen the thermistor voltage is below the reference threshold after the delay, an external temperature fail condition exists. to set the external over- temperature limit, set the value of r x resistor to the 12 times the resistance of the thermistor at the over-temp threshold. the temp3v output pin also turns on when the microcontroller sets the ao3:ao 0 bits to select that the external temperature voltage. this causes the tempi voltage to be placed on ao and activates (after 1ms) the over-temperature detection. as long as the ao3:ao0 bits point to the external temperature, the temp3v output remains on. because of the manual scan of the temperature, it may be desired to turn off the automatic scan, although they can be used at the same time without interference. to turn off the automatic scan, set the atmpoff bit. the microcontroller can over-ride both the automatic temperature scan and the microcontroller controlled temperature scan by setting t he temp3on configuration bit. this turns on the temp3v output to keep the temperature control voltage on all the time, for a continuous monitoring of an over-temperature condition. this likely will consume a significant amount of current, so this feature is usually used for special or test purposes. protection as a default, when the ISL94200 detects an internal or external over-temperature condit ion, the fets are turned off, and the iot bit or xot bit (respectively) is set. figure 4. load monitor circuit vss ldmonen vmon v ref ldfail ISL94200 p- = 1 if vmon >v vmonh = 0 if vmon ? v vmon vss p+ r l open power fets r 1 ISL94200
20 fn6718.0 july 3, 2008 turning off the fets in the event of an over-temperature condition prevents continued disc harge or charge of the cells when they are over heated. in the event of an automatic over-temperature condition the fets are held off until the temperature drops back below the temperature recovery threshol d. during this temperature shutdown period, the microcontroller can monitor the internal temperature through the anal og output pin (ao), but any writes to the cfet or dfet bits are ignored the automatic response to an in ternal over-temperature is prevented by setting the disits d bit to ?1?. the automatic response to an external ove r-temperature is prevented by setting the disxtsd bit to ?1?. in either case, it is important for the microcontroller to monitor the internal and external temperature to prot ect the pack and the electronics in an over-temperature condition. analog multiplexer selection the ISL94200 devices can be used to externally monitor individual battery cell voltages and temperatures. each quantity can be monitored at the analog output pin (ao). the desired voltage is selected using the i 2 c interface and the ao3:ao0 bits. see figure 6. voltage monitoring since the voltage on each of th e li-ion cells are normally higher than the regulated supp ly voltage, and since the voltages on the upper cells is much higher than is tolerated by a microcontroller, it is ne cessary to both level shift and divide the voltage before it can be monitored by the microcontroller or an external a/d converter. to get into the voltage range required by the external circuits, the voltage level shifter divides the cell voltage by 2 and references it to vss. therefore, a li-ion cell wi th a voltage of 4.2v becomes a voltage of 2.1v on the ao pin. temperature monitoring the voltage representing the exte rnal temperature applied at the tempi terminal is directed to the ao terminal through a mux, as selected by the ao control bits (see figures 5 and 6). the external temperature voltage is not divided by 2 as are the cell voltages. instead it is a direct reflection of the voltage at the tempi pin. a similar operation occurs when monitoring the internal temperature through the ao output, except there is no external ?calibration? of t he voltage associated with the internal temperature. for the internal temperature monitoring, the voltage at the ou tput is linear with respect to temperature. see ?operating specifications? for information about the output voltage at +25c and the output slope relative to temperature on page 6. ao rgo temp3v tempi vss i 2 c mux i 2 c temp monitor temp fail indicator figure 5. external temperature monitoring and control vss (on) registers tmp3on ao3:ao0 decode osc atmpoff 508ms 4ms to c xot 12r r 1ms delay external ISL94200 ext temp r x charge oc discharge oc discharge sc overcurrent protection circuits ao vcell2 vss scl i 2 c figure 6. analog output monitoring diagram regs ao3:ao0 decode vcell1 vcell6 vc7/vcc sda 2 level shift level shift level shift level shift tempi int temp mux ext temp. mux ISL94200
21 fn6718.0 july 3, 2008 external vmon/cfet protection mechanisms when there is a single charge/discharge path, a blocking diode is recommended in the vmon to p- path in ISL94200 solution. see d 1 in figure 7. this diode is to protect against a negative voltage on the vmon pin that can occur when the fets are off and the charger connects to the pack. this diode is not needed when there is a separate charge and discharge path, because the voltages on p- (discharge) are likely always positive. the diode also is not needed if the differential between the minimum pack voltage and maximum charger voltage does not exceed 22v. when the pack is designed with a single set of charge/discharge fets, the ISL94200 cfet pin should be protected in the even t of an over-current or short circuit shutdown. when this happens, the fet opens suddenly. the flyback voltage from the motor windings could exceed the maximum input voltage on the cfet pin. so, it is recommended that an additional external series diode be placed between the cfet pin of the ISL94200 and the gate of the charge fet. see diode d 3 in figure 7. this will reduce the cfet gate voltage, but not significantly. finally, to protect the charge fet itself in the event of a large negative voltage on the pack- pin, zener diode d 4 is added. the large negative voltage can occur when the p- pin goes significantly negative, while the cfet pin is being internally clamped at vss. the zener voltage of d4 should be less than the v gs (max) specification of the fet. user flags the ISL94200 contains four flags in the register area that the microcontroller can use for general purpose indicators. these bits are designated uflg3, uflg2, uflg1, and uflg0. the microcontroller can set or reset these bits by writing into the appropriate register. the user flag bits are battery backed up, so the contents remain even after exiting a sleep mode. however, if the microcontroller sets the por bit to force a power on reset, all of the user flags will also be reset. in addition, if the voltage on cell-1 ever drops below the por voltage, the contents of the user flags (as well as all other register values) could be lost. serial interface interface conventions the device supports a bidirect ional bus oriented protocol. the protocol defines any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. the device controlling the transfer is called the master and the device being controlled is called the slave. the master always initiates data transfers, and provides the clock for both transmit and receive operations. therefore, the ISL94200 devices operate as slaves in all applications. when sending or receiving data, the convention is the most significant bit (msb) is sent firs t. so, the first address bit sent is bit 7. clock and data data states on the sda line can change only while scl is low. sda state changes during scl high are reserved for indicating start and stop conditions. see figure 8. start condition all commands are preceded by the start condition, which is a high to low transition of sda when scl is high. the device continuously monitors the sda and scl lines for the start condition and will not respond to any command until this condition has been met. see figure 9. stop condition all communications must be terminated by a stop condition, which is a low to high transition of sda when scl is high. the stop condition is also used to place the device into the standby power mode after a read sequence. a stop condition is only issued afte r the transmitting device has released the bus. see figure 9. acknowledge acknowledge is a software convention used to indicate successful data transfer. the transmitting device, either master or slave, releases the bus after transmitting eight bits. during the ninth clock cycle, the receiver pulls the sda line low to acknowledge that it received the eight bits of data. see figure 10. the device responds with an acknowledge after recognition of a start condition and the correct slave byte. if a write operation is selected, the device responds with an acknowledge after the receipt of each subsequent eight bits. the device acknowledges all incoming data and address bytes, except for the slave byte when the contents do not match the device?s internal slave address. pack- pack+ ISL94200 cfet dfet d 3 d 4 d 1 1m vmon figure 7. use of a diodes for protecting the cfet and vmon pins 10m ISL94200
22 fn6718.0 july 3, 2008 in the read mode, the device transmits eight bits of data, releases the sda line, then monitor the line for an acknowledge. if an acknowledge is detected and no stop condition is generated by the master, the device will continues to transmit data. the device terminates further data transmissions if an acknowledge is not detected. the master must then issue a stop condition to return the device to standby mode and place the device into a known state . write operations for a write operation, the devic e requires a slave byte and an address byte. the slave byte specifies the particular device on the i 2 c bus that the master is writing to. the address specifies one of the registers in that device. after receipt of each byte, the device responds with an acknowledge, and awaits the next eight bits from the master. after the acknowledge, following the transfer of data, the master terminates the transfer by generating a stop condition. see figure 11. when receiving data from the master, the value in the data byte is transferred into the register specified by the address byte on the falling edge of the clock following the 8th data bit. after receiving the acknowledge after the data byte, the device automatically increm ents the address. so, before sending the stop bit, the mast er may send additional data to the device without re-sending t he slave and address bytes. after writing to address 0ah, the address ?wraps around? to address 0. do not continue to write to addresses higher than address 08h, since these add resses access registers that are reserved. writing to these locations can result in unexpected device operation. read operations read operations are initiated in the same manner as write operations with the host sendi ng the address where the read is to start (but no data). then, the host sends an ack, a repeated start, and the slave byte with the lsb = 1. after the device acknowledges the slave byte, the device sends out one bit of data for each master clock. after the slave sends eight bits to the master, t he master sends a nack (not acknowledge) to the device, to indicate the data transfer is complete, then the master sends a stop bit. see figure 12. after sending the eighth data bi t to the master, the device automatically increments its internal address pointer. so the master, instead of sending a nack and the stop bit, can send additional clocks to read the contents of the next register - without sending another slave and address byte. if the last address read or wr itten is known, the master can initiate a current address read. in this case, only the slave byte is sent before data is returned. (see figure 12.) . register protection the discharge set, charge set, and feature set configuration registers are write protected on initial power up. in order to write to these r egisters it is necessary to set a bit to enable each one. these write enable bits are in the write enable register (address 08h). write the fseten bit (addr 8:bit 7) to ?1? to enable changes to the data in the feature set register (address 7). scl sda data stable data change data stable figure 8. valid data changes on i 2 c bus scl sda start stop figure 9. i 2 c start and stop bits 8 1 9 data output from transmitter data output from receiver start acknowledge figure 10. acknowledge response from receiver scl from master 0 0101 00 0 s t a r t s t o p slave byte register address data a c k a c k a c k sda bus signals from the slave signals from the master figure 11. write sequence ISL94200: slave byte = 50h ISL94200
23 fn6718.0 july 3, 2008 write the chseten bit (addr 8:bit 6) to ?1? to enable changes to the data in the f eature set register (address 6). write the disseten bit (addr 8:bit 5) to ?1? to enable changes to the data in the f eature set register (address 5). the microcontroller can reset these bits back to zero to prevent inadvertent writes th at change the operation of the pack. operation state machine figure 13 shows a device state machine which defines how the ISL94200 responds to various conditions. 1 0101 00 0 s t a r t s t o p slave byte data a c k n a c k figure 12. read sequence ISL94200: slave byte = 010100xh 0 0101 00 0 s t a r t slave byte register address a c k a c k sda bus signals from the slave signals from the master 1 0101 00 0 s t a r t s t o p slave byte data a c k n a c k random read current address read ISL94200
24 fn6718.0 july 3, 2008 power fails and one or more of the supplies, vcc, v cell1 , v cell2 , and v cell3 do not meet minimum voltage requirements wkup goes above or below threshold (edge triggered). or, sleep bit is set to ?0? i 2 c interface is disabled. biasing is disabled. all registers set to default values (all ?0?) power down state i 2 c interface is enabled. biasing is enabled. voltage regulator is enabled. power up state voltage regulator is on logic and registers are powered by rgo cfet, dfet outputs are off. (require an external command to turn on) charge and discharge current protection circuits and temperature protection circuits are active (default). overcurrent conditions force power fets to turn off. over-temperature conditions force power fets outputs to turn off. voltage and temperature monitoring circuits are awaiting external control. main operating state power is applied and all of the supplies, vcc, v cell1 , v cell2 , and v cell3 meet minimum voltage requirements voltage regulator is off biasing is off logic and registers are powered by v cell1 cfet, dfet outputs are off. charge and discharge current protection circuits all off. voltage and temperature monitoring circuits are off. i 2 c communication is active (if vcell1 voltage is high enough to operate with the external device.) sleep state sleep bit is set to ?1? figure 13. device operation state machine ISL94200
25 fn6718.0 july 3, 2008 applications circuits the following application circuits are ideas to consider when developing a battery-pack implementation. there are many more ways that the pack can be designed. also, refer to the isl9208 or isl9216 application guides for additional circuit design guidelines. figure 14. 7-cell application ci rcuit integrated charge/discharge b- v ss vcell4 vcell1 vcell2 vcell3 vcell5 vcell6 dsense csense ISL94200 vc7/vcc dsref minimize length maximize gauge p- f reset a/d input v cc i/o gp leds 1f i/o resistors optional chrg scl sda wkup rgo rgc temp3v tempi therm cfet dfet ao vmon int scl sda p+ 16v (ISL94200
26 fn6718.0 july 3, 2008 figure 15. 7-cell application ci rcuit separate charge/discharge b- v ss vcell4 vcell1 vcell2 vcell3 vcell5 vcell6 dsense csense optional ISL94200 vc7/vcc dsref minimize length maximize gauge p- f reset a/d input v cc i/o gp leds 1f i/o single wire interface not needed during discharge optional resistors optional chg chrg scl sda wkup rgo rgc temp3v tempi therm cfet dfet ao vmon int scl sda 16v 1.8m 200k 100 3.6v 1.2m 0.1f 4.7f 500 0.47f ISL94200
27 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn6718.0 july 3, 2008 figure 16. 7-cell application circuit with sw itch wake-up and separate charge/discharge b- v ss vcell4 vcell1 vcell2 vcell3 vcell5 vcell6 dsense csense optional ISL94200 vc7/vcc dsref minimize length maximize gauge p- f reset a/d input v cc i/o gp leds 1f i/o single wire interface not needed during discharge optional resistors optional sw chg 825k chrg scl sda wkup rgo rgc temp3v tempi therm cfet dfet ao vmon int scl sda 16v 100 3.6v trigger in one of these locations 10v 0.1f 4.7f 500 ISL94200
28 fn6718.0 july 3, 2008 ISL94200 package outline drawing l24.4x4d 24 lead quad flat no-lead plastic package rev 2, 10/06 0 . 90 0 . 1 5 c 0 . 2 ref typical recommended land pattern 0 . 05 max. ( 24x 0 . 6 ) detail "x" ( 24x 0 . 25 ) 0 . 00 min. ( 20x 0 . 5 ) ( 2 . 50 ) side view ( 3 . 8 typ ) base plane 4 top view bottom view 7 12 24x 0 . 4 0 . 1 13 4.00 pin 1 18 index area 24 19 4.00 2.5 0.50 20x 4x see detail "x" - 0 . 05 + 0 . 07 24x 0 . 23 2 . 50 0 . 15 pin #1 corner (c 0 . 25) 1 seating plane 0.08 c 0.10 c c 0.10 m c a b a b (4x) 0.15 located within the zone indicated. the pin #1 indentifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. dimension b applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes:

▲Up To Search▲

Price & Availability of ISL94200

	To Download ISL94200 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .